There exists a continuing need to improve semiconductor device performance and further scale semiconductor devices. A characteristic that limits scalability and device performance is electron and hole mobility, also referred to as channel mobility, throughout the channel region of transistors. As devices continue to shrink in size, the channel region for transistors continues to also shrink in size, which can limit channel mobility. One technique that may improve scaling limits and device performance is to introduce strain into the channel region, which can improve electron and hole mobility. Different types of strain, including expansive strain, uniaxial tensile strain, and compressive strain, have been introduced to channel regions of various types of transistors in order to determine their affect on electron and/or hole mobility. For some devices, types of strain improve mobility whereas other degrade mobility.
FIG. 1 is a prior art cross sectional view of an NMOS transistor 100 at a stage of fabrication wherein a compressive stress is introduced by a cap-annealing process. The transistor 100 includes a channel region 101, source and drain active regions 102 and 103, a gate oxide layer 104, sidewall spacers 105, and a polysilicon gate 106. After the active regions have been formed by implanting a suitable dopant such as arsenic, a silicon dioxide capping layer 108 is deposited over/on the transistor via a chemical vapor deposition process. Generally, the temperature of deposition should be lower than the phase transition temperature of amorphous silicon. Then, a rapid thermal anneal is performed at a relatively high temperature. The capping layer 108 is then removed and silicide regions (not shown) are typically formed on the active regions 102 and 103, and the polysilicon gate 106. A suitable silicide process is a conventional Co salicide process.
Compressive stress from the polysilicon gate 106 is enhanced by the annealing process described above and introduces tensile stress across the channel region 101. This tensile stress can improve the performance of the transistor 100 by improving hole and electron mobility in the channel region 101. The cap-annealing process described supra can show improvement for NMOS devices.
The above mechanism can improve channel mobility despite its identified limitations and drawbacks. In order to obtain further shrinkage in device dimensions, it is desirable that additional mechanisms are obtained that further improve channel mobility by using different CVD films with specified physical properties.